clk: qcom: mdss: hdmi: increase delays to fix 20nm PLL lock failures
Introduce minor delays in HDMI PHY sequence to ensure that
PHY is ready before failing with a timeout.
Change-Id: I8e9adf542b60e63c0c28d314afd5ac61fa64d1b2
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
diff --git a/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c b/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c
index 742f639..40417f5 100644
--- a/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c
+++ b/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c
@@ -686,15 +686,15 @@
struct mdss_pll_resources *io = vco->priv;
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000000);
- udelay(1);
+ udelay(100);
/* memory barrier */
mb();
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000003);
- udelay(1);
+ udelay(100);
/* memory barrier */
mb();
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000009);
- udelay(1);
+ udelay(100);
/* memory barrier */
mb();
@@ -704,7 +704,7 @@
do {
ready_poll = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_RESET_SM);
time_out_loop++;
- udelay(1);
+ udelay(10);
} while (((ready_poll & (1 << 6)) == 0) &&
(time_out_loop < time_out_max));
if (time_out_loop >= time_out_max)