tree bf1cea618ef9380cdce9cfea8897da9fb961787b
parent 620879c9e33262426db0ade650be5d7a2046377b
author Catalin Marinas <catalin.marinas@arm.com> 1170683260 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1170946164 +0000

[ARM] 4128/1: Architecture compliant TTBR changing sequence

On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>