OMAP: DSS2: DISPC: Fix minimum PCD value
The current driver had a hardcoded minimum value of 2 for pixel clock
divisor (PCD). This doesn't seem to be right.
OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted
pixel clock (IPC) is off.
OMAP3 TRM says the same, but also in the register descriptions that PCD
value 1 is invalid.
OMAP2 TRM says PCD 2 is the minimum.
OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to
work fine.
This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to
find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and
1 for OMAP3/4.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
3 files changed