clk: qcom: mdss: add support for HDMI autopll calculations
Automatically calculate the register
values needed for HDMI PLL based on the
pixel clock.
Change-Id: I6fbe519e0316c3f9cc12cd0afd5aa08a90deed7d
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
diff --git a/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c b/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c
index d72115dc..e866735 100644
--- a/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c
+++ b/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c
@@ -28,37 +28,6 @@
#define HDMI_PHY_CMD_SIZE 68
#define HDMI_PHY_CLK_SIZE 97
-/* hdmi phy registers */
-enum {
- CALC_QSERDES_COM_SYSCLK_EN_SEL_TXBAND = 0,
- CALC_QSERDES_COM_DIV_REF1,
- CALC_QSERDES_COM_DIV_REF2,
- CALC_QSERDES_COM_KVCO_COUNT1,
- CALC_QSERDES_COM_KVCO_COUNT2,
- CALC_QSERDES_COM_KVCO_CAL_CNTRL,
- CALC_QSERDES_COM_KVCO_CODE,
- CALC_QSERDES_COM_VREF_CFG3,
- CALC_QSERDES_COM_VREF_CFG4,
- CALC_QSERDES_COM_VREF_CFG5,
- CALC_QSERDES_COM_PLL_IP_SETI,
- CALC_QSERDES_COM_PLL_CP_SETI,
- CALC_QSERDES_COM_PLL_IP_SETP,
- CALC_QSERDES_COM_PLL_CP_SETP,
- CALC_QSERDES_COM_PLL_CRCTRL,
- CALC_QSERDES_COM_DIV_FRAC_START1,
- CALC_QSERDES_COM_DIV_FRAC_START2,
- CALC_QSERDES_COM_DIV_FRAC_START3,
- CALC_QSERDES_COM_DEC_START1,
- CALC_QSERDES_COM_DEC_START2,
- CALC_QSERDES_COM_PLLLOCK_CMP1,
- CALC_QSERDES_COM_PLLLOCK_CMP2,
- CALC_QSERDES_COM_PLLLOCK_CMP3,
- CALC_QSERDES_COM_PLLLOCK_CMP_EN,
- CALC_QSERDES_COM_RESETSM_CNTRL,
- CALC_HDMI_PHY_MODE,
- CALC_MAX
-};
-
/* Set to 1 for auto KVCO cal; set to 0 for fixed value */
#define HDMI_PHY_AUTO_KVCO_CAL 1
@@ -418,342 +387,12 @@
#define HDMI_PLL_POLL_MAX_READS 2500
#define HDMI_PLL_POLL_TIMEOUT_US 50
+#define HDMI_PLL_REF_CLK_RATE 192ULL
+#define HDMI_PLL_DIVISOR 10000000000ULL
+#define HDMI_PLL_DIVISOR_32 100000U
+#define HDMI_PLL_MIN_VCO_CLK 160000000ULL
+#define HDMI_PLL_TMDS_MAX 800000000U
-static u32 clk_tbl[HDMI_PHY_CLK_SIZE] = {
- 297000000, 268500000, 148500000, 74250000, 27000000, 27027000,
- 25200000, 108108000, 54054000, 25175000, 31500000, 33750000,
- 35500000, 36000000, 40000000, 49500000, 50000000, 56250000,
- 65000000, 68250000, 71000000, 72000000, 73250000, 75000000,
- 78750000, 79500000, 83500000, 85500000, 88750000, 94500000,
- 101000000, 102250000, 106500000, 108000000, 115500000, 117500000,
- 119000000, 121750000, 122500000, 135000000, 136750000, 140250000,
- 146250000, 148250000, 25175000, 31469000, 33784000, 37762000,
- 37800000, 40500000, 40541000, 44900000, 73515000, 74176000,
- 91894000, 92720000, 92813000, 110272000, 111264000, 111375000,
- 118681000, 118800000, 140250000, 148352000, 154000000, 156000000,
- 157000000, 157500000, 162000000, 175500000, 178022000, 178200000,
- 179500000, 182750000, 185440000, 185625000, 187000000, 187250000,
- 189000000, 193250000, 202500000, 204750000, 208000000, 214750000,
- 218250000, 222527000, 222750000, 229500000, 234000000, 245250000,
- 245500000, 261000000, 268250000, 281250000, 288000000, 296703000,
- 340000000,
-};
-
-/* one to one mapping with clk_tbl */
-static u32 clk_settings[CALC_MAX][HDMI_PHY_CLK_SIZE] = {
- { /* CALC_QSERDES_COM_SYSCLK_EN_SEL_TXBAND */
- 0x4A, 0x4A, 0x5A, 0x6A, 0x7A, 0x7A, 0x7A, 0x5A, 0x6A, 0x7A,
- 0x7A, 0x7A, 0x7A, 0x7A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A,
- 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x5A, 0x5A, 0x5A, 0x5A,
- 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A,
- 0x5A, 0x5A, 0x5A, 0x5A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x6A,
- 0x6A, 0x6A, 0x6A, 0x6A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A,
- 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x4A, 0x4A,
- 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A,
- 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A,
- 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A
- },
- { /* CALC_QSERDES_COM_DIV_REF1 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- },
- { /* CALC_QSERDES_COM_DIV_REF2 */
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00
- },
- { /* CALC_QSERDES_COM_KVCO_COUNT1 */
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
- 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x00
- },
- { /* CALC_QSERDES_COM_KVCO_COUNT2 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- },
- { /* CALC_QSERDES_COM_KVCO_CAL_CNTRL */
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00
- },
- { /* CALC_QSERDES_COM_KVCO_CODE */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F
- },
- { /* CALC_QSERDES_COM_VREF_CFG3 */
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00
- },
- { /* CALC_QSERDES_COM_VREF_CFG4 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- },
- { /* CALC_QSERDES_COM_VREF_CFG5 */
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10
- },
- { /* CALC_QSERDES_COM_PLL_IP_SETI */
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03
- },
- { /* CALC_QSERDES_COM_PLL_CP_SETI */
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x2F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x2F, 0x2F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x2F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x2F, 0x2F, 0x3F, 0x3F
- },
- { /* CALC_QSERDES_COM_PLL_IP_SETP */
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03
- },
- { /* CALC_QSERDES_COM_PLL_CP_SETP */
- 0x17, 0x1F, 0x17, 0x17, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x17, 0x17, 0x17, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x17, 0x1F, 0x1F, 0x1F, 0x17, 0x17, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x17, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x17, 0x17, 0x17, 0x17, 0x17, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x17, 0x17
- },
- { /* CALC_QSERDES_COM_PLL_CRCTRL */
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0x77, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
- 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB
- },
- { /* CALC_QSERDES_COM_DIV_FRAC_START1 */
- 0x80, 0x80, 0x80, 0x80, 0x80, 0xE6, 0x80, 0xE6, 0xE6, 0xAB,
- 0x80, 0x80, 0xD5, 0x80, 0xAB, 0x80, 0xD5, 0x80, 0xD5, 0x80,
- 0xD5, 0x80, 0xD5, 0x80, 0x80, 0x80, 0xD5, 0x80, 0xD5, 0x80,
- 0xAB, 0xD5, 0x80, 0x80, 0x80, 0xAB, 0xAB, 0xD5, 0xD5, 0x80,
- 0xD5, 0x80, 0x80, 0xAB, 0xAB, 0xF7, 0xA2, 0xBC, 0x80, 0x80,
- 0xEF, 0xD5, 0x80, 0xC4, 0x89, 0xAB, 0x91, 0xEF, 0xB3, 0x80,
- 0xA2, 0x80, 0x80, 0xC4, 0xD5, 0x80, 0xD5, 0x80, 0x80, 0x80,
- 0xA2, 0x80, 0xAB, 0xD5, 0xAB, 0x80, 0xAB, 0xD5, 0x80, 0xD5,
- 0x80, 0x80, 0xAB, 0xAB, 0x80, 0xA2, 0x80, 0x80, 0x80, 0x80,
- 0xAB, 0x80, 0xD5, 0x80, 0x80, 0xB3, 0xAB
- },
- { /* CALC_QSERDES_COM_DIV_FRAC_START2 */
- 0x80, 0x80, 0x80, 0x80, 0x80, 0xCC, 0x80, 0xCC, 0xCC, 0xD5,
- 0x80, 0x80, 0xAA, 0x80, 0xD5, 0x80, 0xAA, 0x80, 0xAA, 0x80,
- 0xAA, 0x80, 0xAA, 0x80, 0x80, 0x80, 0xAA, 0x80, 0xAA, 0x80,
- 0xD5, 0xAA, 0x80, 0x80, 0x80, 0xD5, 0xD5, 0xAA, 0xAA, 0x80,
- 0xAA, 0x80, 0x80, 0xD5, 0xD5, 0xEE, 0xC4, 0xF7, 0x80, 0x80,
- 0xDD, 0xAA, 0x80, 0x88, 0x91, 0xD5, 0xE2, 0xDD, 0xE6, 0xC0,
- 0x84, 0x80, 0x80, 0x88, 0xAA, 0x80, 0xAA, 0x80, 0x80, 0x80,
- 0x84, 0x80, 0xD5, 0xEA, 0xD5, 0xE0, 0xD5, 0xEA, 0x80, 0xEA,
- 0x80, 0xC0, 0xD5, 0x95, 0xC0, 0xE4, 0xC0, 0x80, 0x80, 0xC0,
- 0xD5, 0x80, 0xEA, 0xC0, 0x80, 0x86, 0xD5
- },
- { /* CALC_QSERDES_COM_DIV_FRAC_START3 */
- 0x56, 0x7B, 0x56, 0x56, 0x50, 0x53, 0x60, 0x53, 0x53, 0x5C,
- 0x68, 0x54, 0x7D, 0x40, 0x6A, 0x64, 0x45, 0x66, 0x6D, 0x46,
- 0x7D, 0x40, 0x53, 0x48, 0x42, 0x74, 0x5F, 0x62, 0x4E, 0x4E,
- 0x66, 0x50, 0x5E, 0x50, 0x4A, 0x4C, 0x7E, 0x5A, 0x73, 0x54,
- 0x4E, 0x43, 0x4B, 0x4D, 0x5C, 0x63, 0x58, 0x6A, 0x70, 0x4C,
- 0x4E, 0x71, 0x65, 0x51, 0x77, 0x52, 0x55, 0x5B, 0x7C, 0x40,
- 0x74, 0x78, 0x43, 0x51, 0x4D, 0x50, 0x71, 0x42, 0x4C, 0x6D,
- 0x57, 0x5A, 0x6F, 0x65, 0x52, 0x55, 0x6C, 0x70, 0x4E, 0x54,
- 0x6F, 0x54, 0x4A, 0x7B, 0x75, 0x7C, 0x40, 0x71, 0x7C, 0x77,
- 0x7B, 0x7E, 0x76, 0x4F, 0x40, 0x51, 0x62
- },
- { /* CALC_QSERDES_COM_DEC_START1 */
- 0xCD, 0xC5, 0xCD, 0xCD, 0xB8, 0xB8, 0xB4, 0xB8, 0xB8, 0xB4,
- 0xC1, 0xC6, 0xC9, 0xCB, 0xA9, 0xB3, 0xB4, 0xBA, 0xC3, 0xC7,
- 0xC9, 0xCB, 0xCC, 0xCE, 0xD2, 0xD2, 0xAB, 0xAC, 0xAE, 0xB1,
- 0xB4, 0xB5, 0xB7, 0xB8, 0xBC, 0xBD, 0xBD, 0xBF, 0xBF, 0xC6,
- 0xC7, 0xC9, 0xCC, 0xCD, 0xB4, 0xC1, 0xC6, 0xCE, 0xCE, 0xAA,
- 0xAA, 0xAE, 0xCC, 0xCD, 0xAF, 0xB0, 0xB0, 0xB9, 0xB9, 0xBA,
- 0xBD, 0xBD, 0xC9, 0xCD, 0xD0, 0xD1, 0xD1, 0xD2, 0xAA, 0xAD,
- 0xAE, 0xAE, 0xAE, 0xAF, 0xB0, 0xB0, 0xB0, 0xB0, 0xB1, 0xB2,
- 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBF,
- 0xBF, 0xC3, 0xC5, 0xC9, 0xCB, 0xCD, 0xD8
- },
- { /*CALC_QSERDES_COM_DEC_START2 */
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
- },
- { /* CALC_QSERDES_COM_PLLLOCK_CMP1 */
- 0xDF, 0xEF, 0xDF, 0xDF, 0xFF, 0x0B, 0xFF, 0x0B, 0x0B, 0xF4,
- 0x7F, 0x3F, 0x2A, 0xFF, 0x54, 0x3F, 0xAA, 0xDF, 0x2A, 0xDF,
- 0x2A, 0xFF, 0x0A, 0x7F, 0x9F, 0x3F, 0xCA, 0x9F, 0xFA, 0x5F,
- 0x14, 0x9A, 0x5F, 0xFF, 0x1F, 0xF4, 0x94, 0xBA, 0x0A, 0x3F,
- 0xFA, 0x6F, 0xEF, 0xC4, 0xF4, 0x72, 0x4E, 0xEF, 0xFF, 0xBF,
- 0xC8, 0x6A, 0x42, 0xCF, 0x49, 0xA1, 0xAB, 0xF1, 0x5B, 0x67,
- 0x72, 0x7F, 0x6F, 0xCF, 0x2A, 0xFF, 0x6A, 0x9F, 0xBF, 0x8F,
- 0x16, 0x1F, 0x64, 0x12, 0xA1, 0xAB, 0xF4, 0x02, 0x5F, 0x42,
- 0x2F, 0xA7, 0x54, 0xBC, 0x77, 0x5B, 0x67, 0xCF, 0xBF, 0x17,
- 0x24, 0x5F, 0xE2, 0x97, 0xFF, 0xCF, 0xD4
- },
- { /* CALC_QSERDES_COM_PLLLOCK_CMP2 */
- 0x3D, 0x37, 0x3D, 0x3D, 0x2C, 0x2D, 0x29, 0x2D, 0x2D, 0x29,
- 0x34, 0x38, 0x3B, 0x3B, 0x21, 0x29, 0x29, 0x2E, 0x36, 0x38,
- 0x3B, 0x3B, 0x3D, 0x3E, 0x41, 0x42, 0x22, 0x23, 0x24, 0x27,
- 0x2A, 0x2A, 0x2C, 0x2C, 0x30, 0x30, 0x31, 0x32, 0x33, 0x38,
- 0x38, 0x3A, 0x3C, 0x3D, 0x29, 0x34, 0x38, 0x3E, 0x3E, 0x21,
- 0x21, 0x25, 0x3D, 0x3D, 0x26, 0x26, 0x26, 0x2D, 0x2E, 0x2E,
- 0x31, 0x31, 0x3A, 0x3D, 0x40, 0x40, 0x41, 0x41, 0x21, 0x24,
- 0x25, 0x25, 0x25, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x28,
- 0x2A, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2E, 0x2F, 0x30, 0x33,
- 0x33, 0x36, 0x37, 0x3A, 0x3B, 0x3D, 0x46
- },
- { /* CALC_QSERDES_COM_PLLLOCK_CMP3 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- },
- { /* CALC_QSERDES_COM_PLLLOCK_CMP_EN */
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11
- },
- { /* CALC_QSERDES_COM_RESETSM_CNTRL */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
- },
- { /* CALC_HDMI_PHY_MODE */
- 0x00, 0x00, 0x01, 0x02, 0x03, 0x03, 0x03, 0x01, 0x02, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x03, 0x03, 0x03, 0x03, 0x03, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- }
-};
static int hdmi_20nm_pll_lock_status(struct mdss_pll_resources *io)
{
@@ -806,25 +445,86 @@
return container_of(clk, struct hdmi_pll_vco_clk, c);
}
+static inline u32 hdmi_20nm_phy_pll_vco_reg_val(struct hdmi_pll_cfg *pll_cfg,
+ u32 tmds_clk)
+{
+ u32 index = 0;
+
+ while (pll_cfg[index].vco_rate < HDMI_PLL_TMDS_MAX &&
+ pll_cfg[index].vco_rate < tmds_clk)
+ index++;
+ return pll_cfg[index].reg;
+}
+
+static void hdmi_20nm_phy_pll_calc_settings(struct mdss_pll_resources *io,
+ struct hdmi_pll_vco_clk *vco, u32 vco_clk, u32 tmds_clk)
+{
+ u32 val = 0;
+ u64 dec_start_val, frac_start_val, pll_lock_cmp;
+
+ /* Calculate decimal and fractional values */
+ dec_start_val = 1000000UL * vco_clk;
+ do_div(dec_start_val, HDMI_PLL_REF_CLK_RATE);
+ do_div(dec_start_val, 2U);
+ frac_start_val = dec_start_val;
+ do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
+ do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
+ frac_start_val *= HDMI_PLL_DIVISOR;
+ frac_start_val = dec_start_val - frac_start_val;
+ frac_start_val *= (u64)(2 << 19);
+ do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
+ do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
+ pll_lock_cmp = dec_start_val;
+ do_div(pll_lock_cmp, 10U);
+ pll_lock_cmp *= 0x800;
+ do_div(pll_lock_cmp, HDMI_PLL_DIVISOR_32);
+ do_div(pll_lock_cmp, HDMI_PLL_DIVISOR_32);
+ pll_lock_cmp -= 1U;
+ do_div(dec_start_val, HDMI_PLL_DIVISOR_32);
+ do_div(dec_start_val, HDMI_PLL_DIVISOR_32);
+
+ /* PLL loop bandwidth */
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->ip_seti, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IP_SETI, val);
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->cp_seti, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CP_SETI, val);
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->cp_setp, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CP_SETP, val);
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->ip_setp, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IP_SETP, val);
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->crctrl, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CRCTRL, val);
+
+ /* PLL calibration */
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START1,
+ 0x80 | (frac_start_val & 0x7F));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START2,
+ 0x80 | ((frac_start_val >> 7) & 0x7F));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START3,
+ 0x40 | ((frac_start_val >> 14) & 0x3F));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START1,
+ 0x80 | (dec_start_val & 0x7F));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START2,
+ 0x02 | (0x01 & (dec_start_val >> 7)));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP1,
+ pll_lock_cmp & 0xFF);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP2,
+ (pll_lock_cmp >> 8) & 0xFF);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP3,
+ (pll_lock_cmp >> 16) & 0xFF);
+}
+
static u32 hdmi_20nm_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
{
- u32 clk_index;
+ u32 tx_band = 0;
struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
struct mdss_pll_resources *io = vco->priv;
+ u64 vco_clk = tmds_clk;
- /* Find clock target for reset sequence */
- for (clk_index = 0; clk_index < HDMI_PHY_CLK_SIZE; clk_index++) {
- if ((clk_tbl[clk_index] >= (tmds_clk - 2000)) &&
- (clk_tbl[clk_index] <= (tmds_clk + 2000))) {
- pr_debug("%s: found clk %d\n", __func__, tmds_clk);
- break;
- }
- }
-
- if (clk_index >= HDMI_PHY_CLK_SIZE) {
- pr_err("%s: pixel clock %d not valid\n", __func__, tmds_clk);
- return -EINVAL;
+ while (vco_clk > 0 && vco_clk < HDMI_PLL_MIN_VCO_CLK) {
+ tx_band++;
+ vco_clk *= 2;
}
/* Initially shut down PHY */
@@ -869,7 +569,7 @@
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL2, 0x01);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYSCLK_EN_SEL_TXBAND,
- clk_settings[CALC_QSERDES_COM_SYSCLK_EN_SEL_TXBAND][clk_index]);
+ 0x4A + (0x10 * tx_band));
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG1, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG2, 0x00);
@@ -881,61 +581,30 @@
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_UP, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_DN, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_CODE,
- clk_settings[CALC_QSERDES_COM_KVCO_CODE][clk_index]);
+ tmds_clk > 300000000 ? 0x3F : 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_COUNT1,
- clk_settings[CALC_QSERDES_COM_KVCO_COUNT1][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_REF1,
- clk_settings[CALC_QSERDES_COM_DIV_REF1][clk_index]);
+ tmds_clk > 300000000 ? 0x00 : 0x8A);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_REF1, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_REF2,
- clk_settings[CALC_QSERDES_COM_DIV_REF2][clk_index]);
+ tmds_clk > 300000000 ? 0x00 : 0x01);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_CAL_CNTRL,
- clk_settings[CALC_QSERDES_COM_KVCO_CAL_CNTRL][clk_index]);
+ tmds_clk > 300000000 ? 0x00 : 0x1F);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG3,
- clk_settings[CALC_QSERDES_COM_VREF_CFG3][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG4,
- clk_settings[CALC_QSERDES_COM_VREF_CFG4][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG5,
- clk_settings[CALC_QSERDES_COM_VREF_CFG5][clk_index]);
+ tmds_clk > 300000000 ? 0x00 : 0x40);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG4, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG5, 0x10);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESETSM_CNTRL,
- clk_settings[CALC_QSERDES_COM_RESETSM_CNTRL][clk_index]);
+ tmds_clk > 300000000 ? 0x80 : 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_CAL_CSR, 0x77);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_TRIM_EN_VCOCALDONE, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_RXTXEPCLK_EN, 0x0C);
- /* PLL loop bandwidth */
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IP_SETI,
- clk_settings[CALC_QSERDES_COM_PLL_IP_SETI][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CP_SETI,
- clk_settings[CALC_QSERDES_COM_PLL_CP_SETI][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IP_SETP,
- clk_settings[CALC_QSERDES_COM_PLL_IP_SETP][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CP_SETP,
- clk_settings[CALC_QSERDES_COM_PLL_CP_SETP][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CRCTRL,
- clk_settings[CALC_QSERDES_COM_PLL_CRCTRL][clk_index]);
+ hdmi_20nm_phy_pll_calc_settings(io, vco, vco_clk, tmds_clk);
- /* PLL calibration */
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START1,
- clk_settings[CALC_QSERDES_COM_DIV_FRAC_START1][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START2,
- clk_settings[CALC_QSERDES_COM_DIV_FRAC_START2][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START3,
- clk_settings[CALC_QSERDES_COM_DIV_FRAC_START3][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START1,
- clk_settings[CALC_QSERDES_COM_DEC_START1][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START2,
- clk_settings[CALC_QSERDES_COM_DEC_START2][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP1,
- clk_settings[CALC_QSERDES_COM_PLLLOCK_CMP1][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP2,
- clk_settings[CALC_QSERDES_COM_PLLLOCK_CMP2][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP3,
- clk_settings[CALC_QSERDES_COM_PLLLOCK_CMP3][clk_index]);
- MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP_EN,
- clk_settings[CALC_QSERDES_COM_PLLLOCK_CMP_EN][clk_index]);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP_EN, 0x11);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CNTRL, 0x07);
/* Resistor calibration linear search */
@@ -949,8 +618,7 @@
/* memory barrier */
mb();
- MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_MODE,
- clk_settings[CALC_HDMI_PHY_MODE][clk_index]);
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_MODE, tx_band);
/* TX lanes (transceivers) power-up sequence */
MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_CLKBUF_ENABLE, 0x03);
@@ -1207,6 +875,71 @@
};
static struct hdmi_pll_vco_clk hdmi_20nm_vco_clk = {
+ .ip_seti = (struct hdmi_pll_cfg[]){
+ {550890000, 0x03},
+ {589240000, 0x07},
+ {689290000, 0x03},
+ {727600000, 0x07},
+ {HDMI_PLL_TMDS_MAX, 0x03},
+ },
+ .cp_seti = (struct hdmi_pll_cfg[]){
+ {34440000, 0x3F},
+ {36830000, 0x2F},
+ {68870000, 0x3F},
+ {73660000, 0x2F},
+ {137730000, 0x3F},
+ {147310000, 0x2F},
+ {275450000, 0x3F},
+ {294620000, 0x2F},
+ {344650000, 0x3F},
+ {363800000, 0x2F},
+ {477960000, 0x3F},
+ {512530000, 0x2F},
+ {550890000, 0x1F},
+ {589240000, 0x2F},
+ {630900000, 0x3F},
+ {650590000, 0x2F},
+ {689290000, 0x1F},
+ {727600000, 0x2F},
+ {HDMI_PLL_TMDS_MAX, 0x3F},
+ },
+ .ip_setp = (struct hdmi_pll_cfg[]){
+ {497340000, 0x03},
+ {512530000, 0x07},
+ {535680000, 0x03},
+ {550890000, 0x07},
+ {574060000, 0x03},
+ {727600000, 0x07},
+ {HDMI_PLL_TMDS_MAX, 0x03},
+ },
+ .cp_setp = (struct hdmi_pll_cfg[]){
+ {36830000, 0x1F},
+ {40010000, 0x17},
+ {73660000, 0x1F},
+ {80000000, 0x17},
+ {147310000, 0x1F},
+ {160010000, 0x17},
+ {294620000, 0x1F},
+ {363800000, 0x17},
+ {497340000, 0x0F},
+ {512530000, 0x1F},
+ {535680000, 0x0F},
+ {550890000, 0x1F},
+ {574060000, 0x0F},
+ {589240000, 0x1F},
+ {727600000, 0x17},
+ {HDMI_PLL_TMDS_MAX, 0x07},
+ },
+ .crctrl = (struct hdmi_pll_cfg[]){
+ {40010000, 0xBB},
+ {40030000, 0x77},
+ {80000000, 0xBB},
+ {80060000, 0x77},
+ {160010000, 0xBB},
+ {160120000, 0x77},
+ {772930000, 0xBB},
+ {HDMI_PLL_TMDS_MAX, 0xFF},
+ },
.c = {
.dbg_name = "hdmi_20nm_vco_clk",
.ops = &hdmi_20nm_vco_clk_ops,
diff --git a/drivers/clk/qcom/mdss/mdss-hdmi-pll.h b/drivers/clk/qcom/mdss/mdss-hdmi-pll.h
index c7a1c14..612b7c4 100644
--- a/drivers/clk/qcom/mdss/mdss-hdmi-pll.h
+++ b/drivers/clk/qcom/mdss/mdss-hdmi-pll.h
@@ -13,11 +13,21 @@
#ifndef __MDSS_HDMI_PLL_H
#define __MDSS_HDMI_PLL_H
+struct hdmi_pll_cfg {
+ unsigned long vco_rate;
+ u32 reg;
+};
+
struct hdmi_pll_vco_clk {
unsigned long rate; /* current vco rate */
unsigned long min_rate; /* min vco rate */
unsigned long max_rate; /* max vco rate */
bool rate_set;
+ struct hdmi_pll_cfg *ip_seti;
+ struct hdmi_pll_cfg *cp_seti;
+ struct hdmi_pll_cfg *ip_setp;
+ struct hdmi_pll_cfg *cp_setp;
+ struct hdmi_pll_cfg *crctrl;
void *priv;
struct clk c;