m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 8a5a1ab..e8042e8 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -14,6 +14,7 @@
#define CPU_NAME "COLDFIRE(m527x)"
#define CPU_INSTR_PER_JIFFY 3
+#include <asm/m52xxacr.h>
/*
* Define the 5270/5271 SIM register set addresses.