MIPS: PCI: Byteswap not needed in little-endian mode
Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which
is a better description for its functionality. When compiled in
big-endian mode, xlp_config_pci_bswap() will configure the PCIe links
to byteswap. In little-endian mode, no swap configuration is needed
for the PCIe controller, and the function is empty.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4802/
Signed-off-by: John Crispin <blogic@openwrt.org>
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
index 140557a..5077148 100644
--- a/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@ -191,7 +191,13 @@
return 0;
}
-static int xlp_enable_pci_bswap(void)
+/*
+ * If big-endian, enable hardware byteswap on the PCIe bridges.
+ * This will make both the SoC and PCIe devices behave consistently with
+ * readl/writel.
+ */
+#ifdef __BIG_ENDIAN
+static void xlp_config_pci_bswap(void)
{
uint64_t pciebase, sysbase;
int node, i;
@@ -222,8 +228,11 @@
reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
}
- return 0;
}
+#else
+/* Swap configuration not needed in little-endian mode */
+static inline void xlp_config_pci_bswap(void) {}
+#endif /* __BIG_ENDIAN */
static int __init pcibios_init(void)
{
@@ -235,7 +244,7 @@
ioport_resource.start = 0;
ioport_resource.end = ~0;
- xlp_enable_pci_bswap();
+ xlp_config_pci_bswap();
set_io_port_base(CKSEG1);
nlm_pci_controller.io_map_base = CKSEG1;