| commit | a2a571b74a3881963d8d09deb272d13afe5b49e3 | [log] [tgz] |
|---|---|---|
| author | Nicolas Ferre <nicolas.ferre@atmel.com> | Fri Oct 22 18:55:39 2010 +0200 |
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | Tue Oct 26 11:32:48 2010 +0200 |
| tree | 491cf5ff56293287906f9cfec785345f24cd2180 | |
| parent | 8aeeda822fbfe7da2d4ea391a9757e9532796598 [diff] |
AT91: pm: make sure that r0 is 0 when dealing with cache operations When using CP15 cache operations (c7), we make sure that Rd (r0) is actually 0 as ARM 926 TRM is saying. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>