| commit | ac8320c471e187d7fdc90f807199ff77c116a668 | [log] [tgz] |
|---|---|---|
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | Tue May 06 11:46:10 2014 +0300 |
| committer | Lee Jones <lee.jones@linaro.org> | Tue Jun 03 08:11:28 2014 +0100 |
| tree | 19052d42fd12b3290a26a2d1c5f99aeba06a5d70 | |
| parent | a58cc84cafa2376a2d5fcdb3d513327a2fb813c2 [diff] |
mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk When the MCLK is 19.2 or 38.4 MHz the HPPLL need to be enabled and can be put in bypass mode. This will fix HPPLL use on boards with 19.2MHz mclk. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>