tree 3a3403726f2f43f5753d3a29619cc32d7639ce07
parent 57b2d68863f281737d8596cb3d76d89d9cc54fd8
author Stephen Warren <swarren@nvidia.com> 1346975253 -0600
committer Mark Brown <broonie@opensource.wolfsonmicro.com> 1346982722 +0800

ASoC: tegra: fix maxburst settings in dmaengine code

The I2S controllers are programmed with an "attention" level of 4 DWORDs.
This must match the configuration passed to the DMA driver, so that when
they burst in data, they don't overflow the available FIFO space. Also,
the burst size is relevant to the destination for playback, and source
for capture, not vice-versa as originally written.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@vger.kernel.org