| commit | a41dc0e841523efe1df7fa5ad48b5e9027a921df | [log] [tgz] |
|---|---|---|
| author | Catalin Marinas <catalin.marinas@arm.com> | Thu Apr 03 17:48:54 2014 +0100 |
| committer | Catalin Marinas <catalin.marinas@arm.com> | Fri May 09 15:47:45 2014 +0100 |
| tree | c162086a45807902dd8c510132f3c3f82603d3e6 | |
| parent | 89ca3b881987f5a4be4c5dbaa7f0df12bbdde2fd [diff] |
arm64: Implement cache_line_size() based on CTR_EL0.CWG The hardware provides the maximum cache line size in the system via the CTR_EL0.CWG bits. This patch implements the cache_line_size() function to read such information, together with a sanity check if the statically defined L1_CACHE_BYTES is smaller than the hardware value. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>