[SPARC]: Try to start getting SMP back into shape.
Todo items:
- IRQ_INPROGRESS flag - use sparc64 irq buckets, or generic irq_desc?
- sun4d
- re-indent large chunks of sun4m_smp.c
- some places assume sequential cpu numbering (i.e. 0,1 instead of 0,2)
Last I checked (with 2.6.14), random programs segfault with dual
HyperSPARC. And with SuperSPARC II's, it seems stable but will
eventually die from a write lock error (wrong lock owner or something).
I haven't tried the HyperSPARC + highmem combination recently, so that
may still be a problem.
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/include/asm-sparc/spinlock.h b/include/asm-sparc/spinlock.h
index e344c98..3350c90 100644
--- a/include/asm-sparc/spinlock.h
+++ b/include/asm-sparc/spinlock.h
@@ -94,7 +94,7 @@
#define __raw_read_lock(lock) \
do { unsigned long flags; \
local_irq_save(flags); \
- __raw_read_lock(lock); \
+ __read_lock(lock); \
local_irq_restore(flags); \
} while(0)
@@ -114,11 +114,11 @@
#define __raw_read_unlock(lock) \
do { unsigned long flags; \
local_irq_save(flags); \
- __raw_read_unlock(lock); \
+ __read_unlock(lock); \
local_irq_restore(flags); \
} while(0)
-extern __inline__ void __raw_write_lock(raw_rwlock_t *rw)
+static inline void __raw_write_lock(raw_rwlock_t *rw)
{
register raw_rwlock_t *lp asm("g1");
lp = rw;
@@ -131,9 +131,28 @@
: "g2", "g4", "memory", "cc");
}
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+ unsigned int val;
+
+ __asm__ __volatile__("ldstub [%1 + 3], %0"
+ : "=r" (val)
+ : "r" (&rw->lock)
+ : "memory");
+
+ if (val == 0) {
+ val = rw->lock & ~0xff;
+ if (val)
+ ((volatile u8*)&rw->lock)[3] = 0;
+ }
+
+ return (val == 0);
+}
+
#define __raw_write_unlock(rw) do { (rw)->lock = 0; } while(0)
#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
#endif /* !(__ASSEMBLY__) */