tree d8434f779724e4d700d1dda0f781264f24a9ba50
parent 04e2eee4b02edcafce96c9c37b31b1a3318291a4
author Vineet Gupta <vgupta@synopsys.com> 1418294116 +0530
committer Vineet Gupta <vgupta@synopsys.com> 1435192218 +0530

ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock

A quad core SMP build could get into hardware livelock with concurrent
LLOCK/SCOND. Workaround that by adding a PREFETCHW which is serialized by
SCU (System Coherency Unit). It brings the cache line in Exclusive state
and makes others invalidate their lines. This gives enough time for
winner to complete the LLOCK/SCOND, before others can get the line back.

The prefetchw in the ll/sc loop is not nice but this is the only
software workaround for current version of RTL.

Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>