| commit | a62d0834dee83994e41fcd0e5b7f10aad3d80de0 | [log] [tgz] |
|---|---|---|
| author | Imre Deak <imre.deak@intel.com> | Thu May 16 14:40:35 2013 +0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Fri May 31 20:54:00 2013 +0200 |
| tree | 3bd1930537c7d8afb5335f4fab878403c738e3bc | |
| parent | 982a38667dd9f175f8dd8a78651426ae6baac463 [diff] |
drm/i915: merge VLV eDP and DP AUX clock divider calculation On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we can calculate for both the clock divider for the 2MHz target rate at the same place. Afterwards we can also replace the is_cpu_edp() check with a check for port A. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>