commit a64725eecfaf63eb6126c4180c6e159f3a613ae9
author Dhaval Patel <pdhaval@codeaurora.org> Thu Feb 09 16:06:03 2017 -0800
committer Dhaval Patel <pdhaval@codeaurora.org> Fri Feb 10 17:59:39 2017 -0800
tree beac6aa01547e057bd869eb4a3c5166c376a3390
parent 96337de3dd60decfe24481ccbce7c5cc1b459783

drm/msm/sde: setup alpha and bit format on qseedv3

Setup valid alpha and bit format on qseedv3 for
RGB formats.

Change-Id: I28d720fecab78771125c3fa533a46f58663666d7
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
index 3ebe6cd..88dc98f 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -597,10 +597,8 @@
 		|| !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk)
 		return;
 
-	if (!scaler3_cfg->enable) {
-		SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, 0x0);
-		return;
-	}
+	if (!scaler3_cfg->enable)
+		goto end;
 
 	op_mode |= BIT(0);
 	op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
@@ -610,9 +608,6 @@
 		op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
 	}
 
-	if (!SDE_FORMAT_IS_DX(sspp->layout.format))
-		op_mode |= BIT(14);
-
 	op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
 	op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
 
@@ -640,10 +635,6 @@
 		_sde_hw_sspp_setup_scaler3_lut(ctx, scaler3_cfg);
 
 	if (ctx->cap->sblk->scaler_blk.version == 0x1002) {
-		if (sspp->layout.format->alpha_enable) {
-			op_mode |= BIT(10);
-			op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
-		}
 		phase_init =
 			((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
 			((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
@@ -651,10 +642,6 @@
 			((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
 		SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT + idx, phase_init);
 	} else {
-		if (sspp->layout.format->alpha_enable) {
-			op_mode |= BIT(10);
-			op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
-		}
 		SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_H + idx,
 			scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
 		SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_V + idx,
@@ -685,6 +672,17 @@
 
 	SDE_REG_WRITE(&ctx->hw, QSEED3_DST_SIZE + idx, dst);
 
+end:
+	if (!SDE_FORMAT_IS_DX(sspp->layout.format))
+		op_mode |= BIT(14);
+
+	if (sspp->layout.format->alpha_enable) {
+		op_mode |= BIT(10);
+		if (ctx->cap->sblk->scaler_blk.version == 0x1002)
+			op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
+		else
+			op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
+	}
 	SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, op_mode);
 }