| commit | a74c52def9ab953c77956a8e93d225621980f54c | [log] [tgz] |
|---|---|---|
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | Wed Apr 02 16:48:45 2014 +0300 |
| committer | Mike Turquette <mturquette@linaro.org> | Thu Jul 31 08:36:58 2014 -0700 |
| tree | f84ef30560279ed4eab59f732f345bee34346f04 | |
| parent | 64aa90f26c06e1cb2aacfb98a7d0eccfbd6c1a91 [diff] |
clk: ti: clk-7xx: Correct ABE DPLL configuration ABE DPLL frequency need to be lowered from 361267200 to 180633600 to facilitate the ATL requironments. The dpll_abe_m2x2_ck clock need to be set to double of ABE DPLL rate in order to have correct clocks for audio. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>