| commit | a755ecb2cd073bb131ad159258e9d18d7f3998a7 | [log] [tgz] |
|---|---|---|
| author | Deepak Katragadda <dkatraga@codeaurora.org> | Mon Nov 28 14:48:56 2016 -0800 |
| committer | Deepak Katragadda <dkatraga@codeaurora.org> | Fri Dec 02 11:37:00 2016 -0800 |
| tree | 9f84caee8a22e6d7c4b00593226690075044d5dc | |
| parent | 24c8b94ea53ede8962740ab3f049fefcdb5c4ae0 [diff] |
clk: Account for deviation in PLL rate configuration during voltage voting Fabia PLLs only have 16 bits to program the fractional divider for the PLL. Hence, there is a difference between the desired rate and the actual rate that the PLL is programmed to. Account for this difference during voltage voting for these clocks. Change-Id: I6daef37bcfd7634c452ebcd0d6fd5c108ae8e027 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>