tree e6d8b940bfa97afebb713a01ad96e31b6ca0de48
parent c947a585ab13f310c9223284dfd502790abd05f9
author Oskar Schirmer <os@emlix.com> 1236180090 +0100
committer Chris Zankel <chris@zankel.net> 1238740876 -0700

xtensa: enforce slab alignment to maximum register width

XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
aligned to this.

Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
(wordsize) for now.  But the S6000 variant will raise this to 16.

Signed-off-by: Oskar Schirmer <os@emlix.com>
Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>