tree a5057395b763726bb1ca34e7a11e9b057ed067e6
parent f19a302247735876e08e95966ff5668e01946972
author Vaibhav Hiremath <hvaibhav@ti.com> 1348099515 -0600
committer Paul Walmsley <paul@pwsan.com> 1348332788 -0600

ARM: AM33XX: cm: Add bit-field width values

The new common clk framework includes basic definitions for mux and
divider clocks.  These definitions depend on shift and width values
instead of the pre-computed masks that the OMAP/AM33XX clk framework
has traditionally used when accessing the register to control the
mux or divisor.

To ease this transition the masks are left intact and
the width field is simply added alongside the shift and mask data.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>