| commit | a8953c52b95167b5d21a66f0859751570271d834 | [log] [tgz] |
|---|---|---|
| author | Ben Skeggs <bskeggs@redhat.com> | Fri Jun 03 14:37:40 2016 +1000 |
| committer | Ben Skeggs <bskeggs@redhat.com> | Tue Jun 07 08:11:14 2016 +1000 |
| tree | 210fe44ee38c2cfcd0741f444e94288dffdb6709 | |
| parent | 77154fd969df749f5bf83f639af19fca199de033 [diff] |
drm/nouveau/disp/sor/gf119: both links use the same training register It appears that, for whatever reason, both link A and B use the same register to control the training pattern. It's a little odd, as the GPUs before this (Tesla/Fermi1) have per-link registers, as do newer GPUs (Maxwell). Fixes the third DP output on NVS 510 (GK107). Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org