| /* |
| * Copyright (C) 2010 Google, Inc. |
| * |
| * This software is licensed under the terms of the GNU General Public |
| * License version 2, as published by the Free Software Foundation, and |
| * may be copied, distributed, and modified under those terms. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| */ |
| |
| #include <linux/err.h> |
| #include <linux/module.h> |
| #include <linux/init.h> |
| #include <linux/platform_device.h> |
| #include <linux/clk.h> |
| #include <linux/io.h> |
| #include <linux/of.h> |
| #include <linux/of_device.h> |
| #include <linux/mmc/card.h> |
| #include <linux/mmc/host.h> |
| #include <linux/mmc/slot-gpio.h> |
| #include <linux/gpio/consumer.h> |
| |
| #include "sdhci-pltfm.h" |
| |
| /* Tegra SDHOST controller vendor register definitions */ |
| #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 |
| #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 |
| #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 |
| #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 |
| #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 |
| |
| #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) |
| #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) |
| #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) |
| #define NVQUIRK_DISABLE_SDR50 BIT(3) |
| #define NVQUIRK_DISABLE_SDR104 BIT(4) |
| #define NVQUIRK_DISABLE_DDR50 BIT(5) |
| |
| struct sdhci_tegra_soc_data { |
| const struct sdhci_pltfm_data *pdata; |
| u32 nvquirks; |
| }; |
| |
| struct sdhci_tegra { |
| const struct sdhci_tegra_soc_data *soc_data; |
| struct gpio_desc *power_gpio; |
| bool ddr_signaling; |
| }; |
| |
| static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) |
| { |
| struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| struct sdhci_tegra *tegra_host = pltfm_host->priv; |
| const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
| |
| if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && |
| (reg == SDHCI_HOST_VERSION))) { |
| /* Erratum: Version register is invalid in HW. */ |
| return SDHCI_SPEC_200; |
| } |
| |
| return readw(host->ioaddr + reg); |
| } |
| |
| static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| { |
| struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| |
| switch (reg) { |
| case SDHCI_TRANSFER_MODE: |
| /* |
| * Postpone this write, we must do it together with a |
| * command write that is down below. |
| */ |
| pltfm_host->xfer_mode_shadow = val; |
| return; |
| case SDHCI_COMMAND: |
| writel((val << 16) | pltfm_host->xfer_mode_shadow, |
| host->ioaddr + SDHCI_TRANSFER_MODE); |
| return; |
| } |
| |
| writew(val, host->ioaddr + reg); |
| } |
| |
| static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| { |
| struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| struct sdhci_tegra *tegra_host = pltfm_host->priv; |
| const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
| |
| /* Seems like we're getting spurious timeout and crc errors, so |
| * disable signalling of them. In case of real errors software |
| * timers should take care of eventually detecting them. |
| */ |
| if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) |
| val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); |
| |
| writel(val, host->ioaddr + reg); |
| |
| if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && |
| (reg == SDHCI_INT_ENABLE))) { |
| /* Erratum: Must enable block gap interrupt detection */ |
| u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); |
| if (val & SDHCI_INT_CARD_INT) |
| gap_ctrl |= 0x8; |
| else |
| gap_ctrl &= ~0x8; |
| writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); |
| } |
| } |
| |
| static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) |
| { |
| return mmc_gpio_get_ro(host->mmc); |
| } |
| |
| static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) |
| { |
| struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| struct sdhci_tegra *tegra_host = pltfm_host->priv; |
| const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
| u32 misc_ctrl; |
| |
| sdhci_reset(host, mask); |
| |
| if (!(mask & SDHCI_RESET_ALL)) |
| return; |
| |
| misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); |
| /* Erratum: Enable SDHCI spec v3.00 support */ |
| if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) |
| misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; |
| /* Don't advertise UHS modes which aren't supported yet */ |
| if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) |
| misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; |
| if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) |
| misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; |
| if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) |
| misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; |
| sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); |
| |
| tegra_host->ddr_signaling = false; |
| } |
| |
| static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) |
| { |
| u32 ctrl; |
| |
| ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && |
| (bus_width == MMC_BUS_WIDTH_8)) { |
| ctrl &= ~SDHCI_CTRL_4BITBUS; |
| ctrl |= SDHCI_CTRL_8BITBUS; |
| } else { |
| ctrl &= ~SDHCI_CTRL_8BITBUS; |
| if (bus_width == MMC_BUS_WIDTH_4) |
| ctrl |= SDHCI_CTRL_4BITBUS; |
| else |
| ctrl &= ~SDHCI_CTRL_4BITBUS; |
| } |
| sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| } |
| |
| static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
| { |
| struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| struct sdhci_tegra *tegra_host = pltfm_host->priv; |
| unsigned long host_clk; |
| |
| if (!clock) |
| return; |
| |
| host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; |
| clk_set_rate(pltfm_host->clk, host_clk); |
| host->max_clk = clk_get_rate(pltfm_host->clk); |
| |
| return sdhci_set_clock(host, clock); |
| } |
| |
| static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, |
| unsigned timing) |
| { |
| struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| struct sdhci_tegra *tegra_host = pltfm_host->priv; |
| |
| if (timing == MMC_TIMING_UHS_DDR50) |
| tegra_host->ddr_signaling = true; |
| |
| return sdhci_set_uhs_signaling(host, timing); |
| } |
| |
| static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) |
| { |
| struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| |
| /* |
| * DDR modes require the host to run at double the card frequency, so |
| * the maximum rate we can support is half of the module input clock. |
| */ |
| return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2; |
| } |
| |
| static const struct sdhci_ops tegra_sdhci_ops = { |
| .get_ro = tegra_sdhci_get_ro, |
| .read_w = tegra_sdhci_readw, |
| .write_l = tegra_sdhci_writel, |
| .set_clock = tegra_sdhci_set_clock, |
| .set_bus_width = tegra_sdhci_set_bus_width, |
| .reset = tegra_sdhci_reset, |
| .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, |
| .get_max_clock = tegra_sdhci_get_max_clock, |
| }; |
| |
| static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { |
| .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
| SDHCI_QUIRK_SINGLE_POWER_WRITE | |
| SDHCI_QUIRK_NO_HISPD_BIT | |
| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
| .ops = &tegra_sdhci_ops, |
| }; |
| |
| static const struct sdhci_tegra_soc_data soc_data_tegra20 = { |
| .pdata = &sdhci_tegra20_pdata, |
| .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | |
| NVQUIRK_ENABLE_BLOCK_GAP_DET, |
| }; |
| |
| static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { |
| .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
| SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
| SDHCI_QUIRK_SINGLE_POWER_WRITE | |
| SDHCI_QUIRK_NO_HISPD_BIT | |
| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
| .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, |
| .ops = &tegra_sdhci_ops, |
| }; |
| |
| static const struct sdhci_tegra_soc_data soc_data_tegra30 = { |
| .pdata = &sdhci_tegra30_pdata, |
| .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | |
| NVQUIRK_DISABLE_SDR50 | |
| NVQUIRK_DISABLE_SDR104, |
| }; |
| |
| static const struct sdhci_ops tegra114_sdhci_ops = { |
| .get_ro = tegra_sdhci_get_ro, |
| .read_w = tegra_sdhci_readw, |
| .write_w = tegra_sdhci_writew, |
| .write_l = tegra_sdhci_writel, |
| .set_clock = tegra_sdhci_set_clock, |
| .set_bus_width = tegra_sdhci_set_bus_width, |
| .reset = tegra_sdhci_reset, |
| .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, |
| .get_max_clock = tegra_sdhci_get_max_clock, |
| }; |
| |
| static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { |
| .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
| SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
| SDHCI_QUIRK_SINGLE_POWER_WRITE | |
| SDHCI_QUIRK_NO_HISPD_BIT | |
| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
| .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, |
| .ops = &tegra114_sdhci_ops, |
| }; |
| |
| static const struct sdhci_tegra_soc_data soc_data_tegra114 = { |
| .pdata = &sdhci_tegra114_pdata, |
| .nvquirks = NVQUIRK_DISABLE_SDR50 | |
| NVQUIRK_DISABLE_DDR50 | |
| NVQUIRK_DISABLE_SDR104, |
| }; |
| |
| static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { |
| .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
| SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
| SDHCI_QUIRK_SINGLE_POWER_WRITE | |
| SDHCI_QUIRK_NO_HISPD_BIT | |
| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
| .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, |
| .ops = &tegra114_sdhci_ops, |
| }; |
| |
| static const struct sdhci_tegra_soc_data soc_data_tegra210 = { |
| .pdata = &sdhci_tegra210_pdata, |
| .nvquirks = NVQUIRK_DISABLE_SDR50 | |
| NVQUIRK_DISABLE_DDR50 | |
| NVQUIRK_DISABLE_SDR104, |
| }; |
| |
| static const struct of_device_id sdhci_tegra_dt_match[] = { |
| { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, |
| { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, |
| { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, |
| { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, |
| { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, |
| {} |
| }; |
| MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); |
| |
| static int sdhci_tegra_probe(struct platform_device *pdev) |
| { |
| const struct of_device_id *match; |
| const struct sdhci_tegra_soc_data *soc_data; |
| struct sdhci_host *host; |
| struct sdhci_pltfm_host *pltfm_host; |
| struct sdhci_tegra *tegra_host; |
| struct clk *clk; |
| int rc; |
| |
| match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); |
| if (!match) |
| return -EINVAL; |
| soc_data = match->data; |
| |
| host = sdhci_pltfm_init(pdev, soc_data->pdata, 0); |
| if (IS_ERR(host)) |
| return PTR_ERR(host); |
| pltfm_host = sdhci_priv(host); |
| |
| tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL); |
| if (!tegra_host) { |
| dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n"); |
| rc = -ENOMEM; |
| goto err_alloc_tegra_host; |
| } |
| tegra_host->ddr_signaling = false; |
| tegra_host->soc_data = soc_data; |
| pltfm_host->priv = tegra_host; |
| |
| rc = mmc_of_parse(host->mmc); |
| if (rc) |
| goto err_parse_dt; |
| |
| tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", |
| GPIOD_OUT_HIGH); |
| if (IS_ERR(tegra_host->power_gpio)) { |
| rc = PTR_ERR(tegra_host->power_gpio); |
| goto err_power_req; |
| } |
| |
| clk = devm_clk_get(mmc_dev(host->mmc), NULL); |
| if (IS_ERR(clk)) { |
| dev_err(mmc_dev(host->mmc), "clk err\n"); |
| rc = PTR_ERR(clk); |
| goto err_clk_get; |
| } |
| clk_prepare_enable(clk); |
| pltfm_host->clk = clk; |
| |
| rc = sdhci_add_host(host); |
| if (rc) |
| goto err_add_host; |
| |
| return 0; |
| |
| err_add_host: |
| clk_disable_unprepare(pltfm_host->clk); |
| err_clk_get: |
| err_power_req: |
| err_parse_dt: |
| err_alloc_tegra_host: |
| sdhci_pltfm_free(pdev); |
| return rc; |
| } |
| |
| static struct platform_driver sdhci_tegra_driver = { |
| .driver = { |
| .name = "sdhci-tegra", |
| .of_match_table = sdhci_tegra_dt_match, |
| .pm = SDHCI_PLTFM_PMOPS, |
| }, |
| .probe = sdhci_tegra_probe, |
| .remove = sdhci_pltfm_unregister, |
| }; |
| |
| module_platform_driver(sdhci_tegra_driver); |
| |
| MODULE_DESCRIPTION("SDHCI driver for Tegra"); |
| MODULE_AUTHOR("Google, Inc."); |
| MODULE_LICENSE("GPL v2"); |