MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions
MIPS R6 added the following four instructions which share the
BLEZ and BLEZL opcodes:
BLEZALC: Compact branch-and-link if GPR rt is <= to zero
BGEZALC: Compact branch-and-link if GPR rt is >= to zero
BLEZC : Compact branch if GPR rt is <= to zero
BGEZC : Compact branch if GPR rt is >= to zero
BGEC : Compact branch if GPR rs is less than or equal to GPR rt
BGEUC : Similar to BGEC but unsigned.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 798204e..c770617 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -552,6 +552,30 @@
if (NO_R6EMU)
break;
case blez_op:
+
+ /*
+ * Compact branches for R6 for the
+ * blez and blezl opcodes.
+ * BLEZ | rs = 0 | rt != 0 == BLEZALC
+ * BLEZ | rs = rt != 0 == BGEZALC
+ * BLEZ | rs != 0 | rt != 0 == BGEUC
+ * BLEZL | rs = 0 | rt != 0 == BLEZC
+ * BLEZL | rs = rt != 0 == BGEZC
+ * BLEZL | rs != 0 | rt != 0 == BGEC
+ *
+ * For real BLEZ{,L}, rt is always 0.
+ */
+ if (cpu_has_mips_r6 && insn.i_format.rt) {
+ if ((insn.i_format.opcode == blez_op) &&
+ ((!insn.i_format.rs && insn.i_format.rt) ||
+ (insn.i_format.rs == insn.i_format.rt)))
+ regs->regs[31] = regs->cp0_epc +
+ dec_insn.pc_inc;
+ *contpc = regs->cp0_epc + dec_insn.pc_inc +
+ dec_insn.next_pc_inc;
+
+ return 1;
+ }
if ((long)regs->regs[insn.i_format.rs] <= 0)
*contpc = regs->cp0_epc +
dec_insn.pc_inc +