diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index 64698ad..208404e 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -240,7 +240,7 @@
 {
 	clk_enable(dd->iclk);
 
-	if (!(dd->flags & BIT(FLAGS_INIT))) {
+	if (!test_bit(FLAGS_INIT, &dd->flags)) {
 		omap_sham_write_mask(dd, SHA_REG_MASK,
 			SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
 
@@ -248,7 +248,7 @@
 					SHA_REG_SYSSTATUS_RESETDONE))
 			return -ETIMEDOUT;
 
-		dd->flags |= BIT(FLAGS_INIT);
+		set_bit(FLAGS_INIT, &dd->flags);
 		dd->err = 0;
 	}
 
@@ -303,7 +303,7 @@
 		return -ETIMEDOUT;
 
 	if (final)
-		ctx->flags |= BIT(FLAGS_FINAL); /* catch last interrupt */
+		set_bit(FLAGS_FINAL, &ctx->flags); /* catch last interrupt */
 
 	len32 = DIV_ROUND_UP(length, sizeof(u32));
 
@@ -336,9 +336,9 @@
 	ctx->digcnt += length;
 
 	if (final)
-		ctx->flags |= BIT(FLAGS_FINAL); /* catch last interrupt */
+		set_bit(FLAGS_FINAL, &ctx->flags); /* catch last interrupt */
 
-	dd->flags |= BIT(FLAGS_DMA_ACTIVE);
+	set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 
 	omap_start_dma(dd->dma_lch);
 
@@ -642,7 +642,7 @@
 
 	if (!err) {
 		omap_sham_copy_hash(req, 1);
-		if (ctx->flags & BIT(FLAGS_FINAL))
+		if (test_bit(FLAGS_FINAL, &ctx->flags))
 			err = omap_sham_finish(req);
 	} else {
 		ctx->flags |= BIT(FLAGS_ERROR);
@@ -666,14 +666,14 @@
 	spin_lock_irqsave(&dd->lock, flags);
 	if (req)
 		ret = ahash_enqueue_request(&dd->queue, req);
-	if (dd->flags & BIT(FLAGS_BUSY)) {
+	if (test_bit(FLAGS_BUSY, &dd->flags)) {
 		spin_unlock_irqrestore(&dd->lock, flags);
 		return ret;
 	}
 	backlog = crypto_get_backlog(&dd->queue);
 	async_req = crypto_dequeue_request(&dd->queue);
 	if (async_req)
-		dd->flags |= BIT(FLAGS_BUSY);
+		set_bit(FLAGS_BUSY, &dd->flags);
 	spin_unlock_irqrestore(&dd->lock, flags);
 
 	if (!async_req)
@@ -1037,13 +1037,10 @@
 	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 	int ready = 0, err = 0;
 
-	if (ctx->flags & BIT(FLAGS_OUTPUT_READY)) {
-		ctx->flags &= ~BIT(FLAGS_OUTPUT_READY);
+	if (test_and_clear_bit(FLAGS_OUTPUT_READY, &ctx->flags))
 		ready = 1;
-	}
 
-	if (dd->flags & BIT(FLAGS_DMA_ACTIVE)) {
-		dd->flags &= ~BIT(FLAGS_DMA_ACTIVE);
+	if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
 		omap_sham_update_dma_stop(dd);
 		if (!dd->err)
 			err = omap_sham_update_dma_start(dd);
@@ -1077,7 +1074,7 @@
 		return IRQ_HANDLED;
 	}
 
-	if (unlikely(ctx->flags & BIT(FLAGS_FINAL)))
+	if (unlikely(test_bit(FLAGS_FINAL, &ctx->flags)))
 		/* final -> allow device to go to power-saving mode */
 		omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
 
@@ -1085,7 +1082,7 @@
 				 SHA_REG_CTRL_OUTPUT_READY);
 	omap_sham_read(dd, SHA_REG_CTRL);
 
-	ctx->flags |= BIT(FLAGS_OUTPUT_READY);
+	set_bit(FLAGS_OUTPUT_READY, &ctx->flags);
 	dd->err = 0;
 	tasklet_schedule(&dd->done_task);
 
@@ -1099,7 +1096,7 @@
 	if (ch_status != OMAP_DMA_BLOCK_IRQ) {
 		pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
 		dd->err = -EIO;
-		dd->flags &= ~BIT(FLAGS_INIT); /* request to re-initialize */
+		clear_bit(FLAGS_INIT, &dd->flags);/* request to re-initialize */
 	}
 
 	tasklet_schedule(&dd->done_task);