| commit | a970449e40789a0056424668da5b56f57569ea73 | [log] [tgz] |
|---|---|---|
| author | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | Sun Feb 09 17:31:47 2014 -0300 |
| committer | Mauro Carvalho Chehab <m.chehab@samsung.com> | Mon Feb 24 13:12:36 2014 -0300 |
| tree | ea77264963dd3c5c9ce814d215f9fbefe944c9e8 | |
| parent | e8e45593c920a05b1f4b9d94738a84039b9b4f22 [diff] |
[media] mt9p031: Add support for PLL bypass When the input clock frequency is out of bounds for the PLL, bypass the PLL and just divide the input clock to achieve the requested output frequency. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>