drm/radeon/kms: add dpm support for SI (v7)
This adds dpm support for SI asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2/gen3 switching
- power containment
- shader power scaling
Set radeon.dpm=1 to enable.
v2: enable hainan support, rebase
v3: guard acpi stuff
v4: fix 64 bit math
v5: fix 64 bit div harder
v6: fix thermal interrupt check noticed by Jerome
v7: attempt fix state enable
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 8e6b23a..649d949 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -719,7 +719,7 @@
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
-static struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
+struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
{
struct ni_power_info *pi = rdev->pm.dpm.priv;
@@ -1471,8 +1471,8 @@
return 0;
}
-static int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
- u32 arb_freq_src, u32 arb_freq_dest)
+int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
+ u32 arb_freq_src, u32 arb_freq_dest)
{
u32 mc_arb_dram_timing;
u32 mc_arb_dram_timing2;
@@ -3488,8 +3488,8 @@
rv770_enable_acpi_pm(rdev);
}
-static void ni_update_current_ps(struct radeon_device *rdev,
- struct radeon_ps *rps)
+void ni_update_current_ps(struct radeon_device *rdev,
+ struct radeon_ps *rps)
{
struct ni_ps *new_ps = ni_get_ps(rps);
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
@@ -3500,8 +3500,8 @@
eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
}
-static void ni_update_requested_ps(struct radeon_device *rdev,
- struct radeon_ps *rps)
+void ni_update_requested_ps(struct radeon_device *rdev,
+ struct radeon_ps *rps)
{
struct ni_ps *new_ps = ni_get_ps(rps);
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
@@ -4192,8 +4192,12 @@
printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
for (i = 0; i < ps->performance_level_count; i++) {
pl = &ps->performance_levels[i];
- printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n",
- pl->sclk, pl->mclk, pl->vddc, pl->vddci);
+ if (rdev->family >= CHIP_TAHITI)
+ printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
+ pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
+ else
+ printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n",
+ pl->sclk, pl->mclk, pl->vddc, pl->vddci);
}
r600_dpm_print_ps_status(rdev, rps);
}