| commit | aa32a955ae46d4117e880417c89a2efcc88579c2 | [log] [tgz] |
|---|---|---|
| author | David Daney <ddaney@caviumnetworks.com> | Thu Oct 07 16:03:40 2010 -0700 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Fri Oct 29 19:08:33 2010 +0100 |
| tree | 538f1564b70d017b224a423d99bc2a0366c1f745 | |
| parent | b93b2abce497873be97d765b848e0a955d29f200 [diff] |
MIPS: Octeon: Update register definitions for CN63XX chips The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>