tree b1787ce0bfe3258b9584f04a9ed49f30bfa6e66b
parent c388eee21ad20929f440d6fae94c995791c5818b
author Peter De Schrijver <pdeschrijver@nvidia.com> 1370440285 +0300
committer Mike Turquette <mturquette@linaro.org> 1370997519 -0700

clk: tegra: allow PLL m,n,p init from SoC files

The m,n,p fields don't have the same bit offset and width across all PLLs.
This patch allows SoC specific files to indicate the offset and width.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>