| commit | 44eeab67416711db9b84610ef18c99a60415dff8 | [log] [tgz] |
|---|---|---|
| author | Ralf Baechle <ralf@linux-mips.org> | Fri Jun 19 15:01:44 2009 +0100 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Wed Jun 24 18:34:39 2009 +0100 |
| tree | e9beb9000be5cd9c17bbb7bc05cd3db1c4cb3f09 | |
| parent | 631330f5847b3f8a7ea67d689e9f7c56833ccaa6 [diff] |
MIPS: Hibernation: Remove SMP TLB and cacheflushing code. We can't perform any flushes on SMP from swsusp_arch_resume because interrupts are disabled. A cross-CPU flush is unnecessary anyway because all but the local CPU have already been disabled. A local flush is not needed either because we didn't change any mappings. So just delete the code. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>