tree 33e3ab959431fce936b581424f1b26bc13cbe820
parent 3bc2913e2cb74aac8af90b46fa251dfb8d854665
author Chris Wilson <chris@chris-wilson.co.uk> 1349098024 +0100
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1349166498 +0200

drm/i915: Actually invalidate the TLB for the SandyBridge HW contexts w/a

A side-effect of commit 7d54a904285b6e780291b91a518267bec5591913
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Aug 10 10:18:10 2012 +0100

    drm/i915: Apply post-sync write for pipe control invalidates

was that only a request to emit invalidate flush would result in the
TLB being invalidated (since it requires synchronisation and so incurs a
performance penalty). However, the stated w/a for hardware contexts is
that the TLBs must be invalidated prior to a MI_SET_CONTEXT, yet the w/a
itself did not request the TLBs to be invalidated...

Note this w/a does not prevent the hard system hang I experience when
using hw contexts (with rc6 enabled) on SNB GT1.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>