ARM: OMAP2: Powerdomain: Add base OMAP2/3 powerdomain code
This patch creates an interface to the powerdomain registers in the
PRM/CM modules on OMAP2/3. This interface is intended to be used by
PM code, e.g., pm.c; not by device drivers directly.
Each powerdomain will be defined in later patches as static
structures. Also defined are dependencies between powerdomains,
used for adding and removing PM_WKDEP and CM_SLEEPDEP bits. The
powerdomain structures are linked into a list at boot by
pwrdm_register(), similar to the OMAP clock code.
The patch adds a Kconfig option, CONFIG_OMAP_DEBUG_POWERDOMAIN, which
when enabled will emit verbose debug messages via pr_debug().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
new file mode 100644
index 0000000..c8f52c6
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -0,0 +1,139 @@
+/*
+ * OMAP2/3 powerdomain control
+ *
+ * Copyright (C) 2007-8 Texas Instruments, Inc.
+ * Copyright (C) 2007-8 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
+#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+#include <asm/atomic.h>
+
+#include <mach/cpu.h>
+
+
+/* Powerdomain basic power states */
+#define PWRDM_POWER_OFF 0x0
+#define PWRDM_POWER_RET 0x1
+#define PWRDM_POWER_INACTIVE 0x2
+#define PWRDM_POWER_ON 0x3
+
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
+ (1 << PWRDM_POWER_ON))
+
+#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
+ (1 << PWRDM_POWER_RET))
+
+#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
+
+
+/*
+ * Number of memory banks that are power-controllable. On OMAP3430, the
+ * maximum is 4.
+ */
+#define PWRDM_MAX_MEM_BANKS 4
+
+/* XXX A completely arbitrary number. What is reasonable here? */
+#define PWRDM_TRANSITION_BAILOUT 100000
+
+struct powerdomain;
+
+/* Encodes dependencies between powerdomains - statically defined */
+struct pwrdm_dep {
+
+ /* Powerdomain name */
+ const char *pwrdm_name;
+
+ /* Powerdomain pointer - resolved by the powerdomain code */
+ struct powerdomain *pwrdm;
+
+ /* Flags to mark OMAP chip restrictions, etc. */
+ const struct omap_chip_id omap_chip;
+
+};
+
+struct powerdomain {
+
+ /* Powerdomain name */
+ const char *name;
+
+ /* the address offset from CM_BASE/PRM_BASE */
+ const s16 prcm_offs;
+
+ /* Used to represent the OMAP chip types containing this pwrdm */
+ const struct omap_chip_id omap_chip;
+
+ /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
+ const u8 dep_bit;
+
+ /* Powerdomains that can be told to wake this powerdomain up */
+ struct pwrdm_dep *wkdep_srcs;
+
+ /* Powerdomains that can be told to keep this pwrdm from inactivity */
+ struct pwrdm_dep *sleepdep_srcs;
+
+ /* Possible powerdomain power states */
+ const u8 pwrsts;
+
+ /* Possible logic power states when pwrdm in RETENTION */
+ const u8 pwrsts_logic_ret;
+
+ /* Number of software-controllable memory banks in this powerdomain */
+ const u8 banks;
+
+ /* Possible memory bank pwrstates when pwrdm in RETENTION */
+ const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
+
+ /* Possible memory bank pwrstates when pwrdm is ON */
+ const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
+
+ struct list_head node;
+
+};
+
+
+void pwrdm_init(struct powerdomain **pwrdm_list);
+
+int pwrdm_register(struct powerdomain *pwrdm);
+int pwrdm_unregister(struct powerdomain *pwrdm);
+struct powerdomain *pwrdm_lookup(const char *name);
+
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
+
+int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
+int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
+int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
+int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
+int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
+int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
+
+int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+
+int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
+int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
+int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
+
+int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
+int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+
+int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+
+int pwrdm_wait_transition(struct powerdomain *pwrdm);
+
+#endif