commit ad8c48ad3bbef078616ed4d2652d362dfd962f09
author Catalin(ux aka Dino) BOIE <util@deuroconsult.ro> Sat Mar 04 12:18:59 2006 -0500
committer Jeff Garzik <jeff@garzik.org> Sat Mar 04 12:18:59 2006 -0500
tree e400f39c22cf68621be51042a860cf402c3a9bd5
parent e72fd96e8ee3ff4dd80757172a4fe49bd92fea9c

Fix io ordering problems in e100

Checking e100.c code against Documentation/io_ordering.txt I found the
following problem:

spin_lock_irq...
write
spin-unlock
e100_write_flush

The attached patch fix the code like this:

spin_lock_irq...
write
e100_write_flush
spin-unlock

Signed-off-by: Catalin BOIE <catab@umbrella.ro>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

drivers/net/e100.c

diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index 24253c8..ed13f72 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -598,8 +598,8 @@
 
 	spin_lock_irqsave(&nic->cmd_lock, flags);
 	writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
-	spin_unlock_irqrestore(&nic->cmd_lock, flags);
 	e100_write_flush(nic);
+	spin_unlock_irqrestore(&nic->cmd_lock, flags);
 }
 
 static void e100_disable_irq(struct nic *nic)
@@ -608,8 +608,8 @@
 
 	spin_lock_irqsave(&nic->cmd_lock, flags);
 	writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
-	spin_unlock_irqrestore(&nic->cmd_lock, flags);
 	e100_write_flush(nic);
+	spin_unlock_irqrestore(&nic->cmd_lock, flags);
 }
 
 static void e100_hw_reset(struct nic *nic)
@@ -1582,8 +1582,8 @@
 	 * interrupt mask bit and the SW Interrupt generation bit */
 	spin_lock_irq(&nic->cmd_lock);
 	writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
-	spin_unlock_irq(&nic->cmd_lock);
 	e100_write_flush(nic);
+	spin_unlock_irq(&nic->cmd_lock);
 
 	e100_update_stats(nic);
 	e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);