| commit | ae48a35c408732413880d0ac0d6467baa5b3d68a | [log] [tgz] |
|---|---|---|
| author | Adam Thomson <Adam.Thomson.Opensource@diasemi.com> | Fri Apr 22 14:16:26 2016 +0100 |
| committer | Mark Brown <broonie@kernel.org> | Fri Apr 22 16:26:19 2016 +0100 |
| tree | 155fc72494d60bb00bcce2ca5dd35b913a398f70 | |
| parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca [diff] |
ASoC: da7218: Update PLL ranges and dividers to improve locking The expected MCLK frequency ranges and the associated dividers are updated to improve PLL locking in a corner scenario, with low MCLK frequency near an input divider change boundary. Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> Signed-off-by: Mark Brown <broonie@kernel.org>