ARM: dts: msm: Configure LMH DCVSh for sdm670
Configure LMH DCVSh hardware parameters like cluster affinity and
interrupts. Associate CPUs with the right LMH DCVSh hardware.
Change-Id: I615b2fb0b435d10bd11b90a988aad756e67ac575
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 310ed35..181de62 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -53,6 +53,7 @@
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_0>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -86,6 +87,7 @@
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_100>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -114,6 +116,7 @@
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_200>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -142,6 +145,7 @@
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_300>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -170,6 +174,7 @@
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_400>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -198,6 +203,7 @@
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_500>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -226,6 +232,7 @@
cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_600>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -254,6 +261,7 @@
cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_700>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;