| /* |
| * IRAM |
| */ |
| #define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ |
| #define MX31_IRAM_SIZE SZ_16K |
| |
| #define MX31_OTG_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x88000) |
| #define MX31_ATA_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x8c000) |
| #define MX31_UART4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb0000) |
| #define MX31_UART5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb4000) |
| |
| #define MX31_MMC_SDHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x04000) |
| #define MX31_MMC_SDHC2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x08000) |
| #define MX31_SIM1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x18000) |
| #define MX31_IIM_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x1c000) |
| |
| #define MX31_CSPI3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x84000) |
| #define MX31_FIRI_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x8c000) |
| #define MX31_SCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xae000) |
| #define MX31_SMN_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xaf000) |
| #define MX31_MPEG4_ENC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc8000) |
| |
| #define MX31_NFC_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x0000) |
| |
| #define MX31_INT_MPEG4_ENCODER 5 |
| #define MX31_INT_FIRI 7 |
| #define MX31_INT_MMC_SDHC2 8 |
| #define MX31_INT_MMC_SDHC1 9 |
| #define MX31_INT_SSI2 11 |
| #define MX31_INT_SSI1 12 |
| #define MX31_INT_MBX 16 |
| #define MX31_INT_CSPI3 17 |
| #define MX31_INT_SIM2 20 |
| #define MX31_INT_SIM1 21 |
| #define MX31_INT_CCM_DVFS 31 |
| #define MX31_INT_USB1 35 |
| #define MX31_INT_USB2 36 |
| #define MX31_INT_USB3 37 |
| #define MX31_INT_USB4 38 |
| #define MX31_INT_MSHC2 40 |
| #define MX31_INT_UART4 46 |
| #define MX31_INT_UART5 47 |
| #define MX31_INT_CCM 53 |
| #define MX31_INT_PCMCIA 54 |
| |
| /* these should go away */ |
| #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR |
| #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR |
| #define UART5_BASE_ADDR MX31_UART5_BASE_ADDR |
| #define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR |
| #define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR |
| #define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR |
| #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR |
| #define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR |
| #define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR |
| #define SCM_BASE_ADDR MX31_SCM_BASE_ADDR |
| #define SMN_BASE_ADDR MX31_SMN_BASE_ADDR |
| #define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR |
| #define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER |
| #define MXC_INT_FIRI MX31_INT_FIRI |
| #define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1 |
| #define MXC_INT_MBX MX31_INT_MBX |
| #define MXC_INT_CSPI3 MX31_INT_CSPI3 |
| #define MXC_INT_SIM2 MX31_INT_SIM2 |
| #define MXC_INT_SIM1 MX31_INT_SIM1 |
| #define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS |
| #define MXC_INT_USB1 MX31_INT_USB1 |
| #define MXC_INT_USB2 MX31_INT_USB2 |
| #define MXC_INT_USB3 MX31_INT_USB3 |
| #define MXC_INT_USB4 MX31_INT_USB4 |
| #define MXC_INT_MSHC2 MX31_INT_MSHC2 |
| #define MXC_INT_UART4 MX31_INT_UART4 |
| #define MXC_INT_UART5 MX31_INT_UART5 |
| #define MXC_INT_CCM MX31_INT_CCM |
| #define MXC_INT_PCMCIA MX31_INT_PCMCIA |