| /* |
| * IRAM |
| */ |
| #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ |
| #define MX35_IRAM_SIZE SZ_128K |
| |
| #define MX35_FEC_BASE_ADDR 0x50038000 |
| #define MX35_OTG_BASE_ADDR 0x53ff4000 |
| #define MX35_NFC_BASE_ADDR 0xbb000000 |
| |
| /* |
| * Interrupt numbers |
| */ |
| #define MX35_INT_OWIRE 2 |
| #define MX35_INT_MMC_SDHC1 7 |
| #define MX35_INT_MMC_SDHC2 8 |
| #define MX35_INT_MMC_SDHC3 9 |
| #define MX35_INT_SSI1 11 |
| #define MX35_INT_SSI2 12 |
| #define MX35_INT_GPU2D 16 |
| #define MX35_INT_ASRC 17 |
| #define MX35_INT_USBHS 35 |
| #define MX35_INT_USBOTG 37 |
| #define MX35_INT_ESAI 40 |
| #define MX35_INT_CAN1 43 |
| #define MX35_INT_CAN2 44 |
| #define MX35_INT_MLB 46 |
| #define MX35_INT_SPDIF 47 |
| #define MX35_INT_FEC 57 |
| |
| /* these should go away */ |
| #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR |
| #define MXC_INT_OWIRE MX35_INT_OWIRE |
| #define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2 |
| #define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3 |
| #define MXC_INT_GPU2D MX35_INT_GPU2D |
| #define MXC_INT_ASRC MX35_INT_ASRC |
| #define MXC_INT_USBHS MX35_INT_USBHS |
| #define MXC_INT_USBOTG MX35_INT_USBOTG |
| #define MXC_INT_ESAI MX35_INT_ESAI |
| #define MXC_INT_CAN1 MX35_INT_CAN1 |
| #define MXC_INT_CAN2 MX35_INT_CAN2 |
| #define MXC_INT_MLB MX35_INT_MLB |
| #define MXC_INT_SPDIF MX35_INT_SPDIF |
| #define MXC_INT_FEC MX35_INT_FEC |