tree ac10053d33f2c91d3594990eae69544aadd680ec
parent e95883b0c65d688469abcb94fd362e5cfa412abf
author Padmanabhan Komanduru <pkomandu@codeaurora.org> 1472648045 +0530
committer Narendra Muppalla <NarendraM@codeaurora.org> 1484942516 -0800

clk: msm: mdss: change DP clock rate in order of KHz

Certain frequencies of DP VCO clock are more than 4.29 GHz
and are not supported by clock framework on 32 bit builds,
since it exceeds the maximum value of unsigned long data type.
To fix this issue, change the DP link clock frequencies in order
of KHz in DP FB driver/MMSS 8998 clock driver/DP PLL driver.

Change-Id: I46d9b5c57f94aa1f10df08c4430b617355a82eec
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Narendra Muppalla <narendram@codeaurora.org>