drm/nouveau/ce: rename from copy (no binary change)
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index 3928439..4a3638e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -64,7 +64,7 @@
case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC : addr = 0x00a0; break;
- case NVDEV_ENGINE_COPY0 : addr = 0x00c0; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x00c0; break;
default:
return -EINVAL;
}
@@ -102,7 +102,7 @@
case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break;
- case NVDEV_ENGINE_COPY0 : engn = 2; addr = 0x00c0; break;
+ case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break;
default:
return -EINVAL;
}
@@ -147,7 +147,7 @@
case NVDEV_ENGINE_MPEG :
case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
case NVDEV_ENGINE_ME :
- case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
+ case NVDEV_ENGINE_CE0 : context |= 0x00300000; break;
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC :
@@ -196,7 +196,7 @@
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
- (1ULL << NVDEV_ENGINE_COPY0) |
+ (1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
@@ -271,7 +271,7 @@
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
- (1ULL << NVDEV_ENGINE_COPY0) |
+ (1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index 2af40b2..1511e38 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -122,8 +122,8 @@
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
- case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
+ case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
@@ -159,8 +159,8 @@
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
- case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
+ case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
@@ -212,8 +212,8 @@
args->v0.pushbuf,
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_COPY0) |
- (1ULL << NVDEV_ENGINE_COPY1) |
+ (1ULL << NVDEV_ENGINE_CE0) |
+ (1ULL << NVDEV_ENGINE_CE1) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_PPP), &chan);
@@ -385,8 +385,8 @@
case NVDEV_ENGINE_MSVLD: engn = 1; break;
case NVDEV_ENGINE_PPP : engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
- case NVDEV_ENGINE_COPY0: engn = 4; break;
- case NVDEV_ENGINE_COPY1: engn = 5; break;
+ case NVDEV_ENGINE_CE0 : engn = 4; break;
+ case NVDEV_ENGINE_CE1 : engn = 5; break;
default:
return -1;
}
@@ -402,8 +402,8 @@
case 1: engn = NVDEV_ENGINE_MSVLD; break;
case 2: engn = NVDEV_ENGINE_PPP; break;
case 3: engn = NVDEV_ENGINE_VP; break;
- case 4: engn = NVDEV_ENGINE_COPY0; break;
- case 5: engn = NVDEV_ENGINE_COPY1; break;
+ case 4: engn = NVDEV_ENGINE_CE0; break;
+ case 5: engn = NVDEV_ENGINE_CE1; break;
default:
return NULL;
}
@@ -552,8 +552,8 @@
{ 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x13, "PCOUNTER" },
{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
- { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
- { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
+ { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
+ { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PDAEMON" },
{}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index b415b30..324008e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -47,12 +47,12 @@
u64 mask;
} fifo_engine[] = {
_(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_COPY2)),
+ (1ULL << NVDEV_ENGINE_CE2)),
_(NVDEV_ENGINE_VP , 0),
_(NVDEV_ENGINE_PPP , 0),
_(NVDEV_ENGINE_MSVLD , 0),
- _(NVDEV_ENGINE_COPY0 , 0),
- _(NVDEV_ENGINE_COPY1 , 0),
+ _(NVDEV_ENGINE_CE0 , 0),
+ _(NVDEV_ENGINE_CE1 , 0),
_(NVDEV_ENGINE_VENC , 0),
};
#undef _
@@ -143,9 +143,9 @@
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW :
return 0;
- case NVDEV_ENGINE_COPY0:
- case NVDEV_ENGINE_COPY1:
- case NVDEV_ENGINE_COPY2:
+ case NVDEV_ENGINE_CE0:
+ case NVDEV_ENGINE_CE1:
+ case NVDEV_ENGINE_CE2:
nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
return 0;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
@@ -183,9 +183,9 @@
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_COPY0:
- case NVDEV_ENGINE_COPY1:
- case NVDEV_ENGINE_COPY2: addr = 0x0000; break;
+ case NVDEV_ENGINE_CE0 :
+ case NVDEV_ENGINE_CE1 :
+ case NVDEV_ENGINE_CE2 : addr = 0x0000; break;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
@@ -415,12 +415,12 @@
{
switch (engn) {
case NVDEV_ENGINE_GR :
- case NVDEV_ENGINE_COPY2: engn = 0; break;
+ case NVDEV_ENGINE_CE2 : engn = 0; break;
case NVDEV_ENGINE_MSVLD: engn = 1; break;
case NVDEV_ENGINE_PPP : engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
- case NVDEV_ENGINE_COPY0: engn = 4; break;
- case NVDEV_ENGINE_COPY1: engn = 5; break;
+ case NVDEV_ENGINE_CE0 : engn = 4; break;
+ case NVDEV_ENGINE_CE1 : engn = 5; break;
case NVDEV_ENGINE_VENC : engn = 6; break;
default:
return -1;
@@ -623,11 +623,11 @@
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x13, "PERF" },
{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
- { 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 },
- { 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 },
+ { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
+ { 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PMU" },
{ 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC },
- { 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 },
+ { 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 },
{}
};
@@ -678,7 +678,7 @@
{ 0x15, "SCC_NB" },
{ 0x16, "SEC" },
{ 0x17, "SSYNC" },
- { 0x18, "GR_COPY" },
+ { 0x18, "GR_CE" },
{ 0x19, "CE2" },
{ 0x1a, "XV" },
{ 0x1b, "MMU_NB" },