| commit | ecbb06594744b72c362cb2252cb5f6de7cf1b394 | [log] [tgz] |
|---|---|---|
| author | Rajendra Nayak <rnayak@ti.com> | Tue Jan 19 17:30:55 2010 -0700 |
| committer | Paul Walmsley <paul@pwsan.com> | Wed Jan 20 13:35:28 2010 -0700 |
| tree | 9073d78f6c122faf2831201189f108f1b263db16 | |
| parent | 0324f59fc945b76337dbc18f4ad4b4383f683ae5 [diff] |
OMAP4: clocks: Fix the clksel_rate struct DPLL divs For all DPLL's the valid dividers are same as the values to be programmed in the register. 0 is an invalid value. The changes are generated by updating the script which autogenerates the file modifed in the patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>