| commit | afff455cf4f2501d30446eefbfd0aecb14b8a0b8 | [log] [tgz] |
|---|---|---|
| author | Andrew Bresticker <abrestic@chromium.org> | Thu Jun 18 17:28:37 2015 -0400 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Dec 17 13:37:57 2015 +0100 |
| tree | 64ace5de7abeb420e49c91f7d4971b238749ba6d | |
| parent | 6b301a059eb2ebed1b12a900e3b21a38e48dd410 [diff] |
clk: tegra: pll: Fix issues with rates for VCO PLLs Without this change clk_get_rate would return the final output rather than the VCO output as it would factor in the pdiv when it shouldn't. This will cause problems for all dividers in the subtree of the VCO PLL. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>