tree f20bacd8b37a19d270528fa6a90578a8b006e2e2
parent b2c3e923110f6ca60ccb30cf4a6bda5211454c4f
author Guennadi Liakhovetski <g.liakhovetski@gmx.de> 1264773086 +0100
committer Mark Brown <broonie@opensource.wolfsonmicro.com> 1265034908 +0000

ASoC: improve MCLKDIV calculation in wm8978, when OPCLK is not used

In case, if OPCLK is not used, and PLL is used for driving the codec, the
choice of PLL output frequency could result in a needlessly imprecise
system clock frequency. Use an iterative process to select a precise
configuration.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>