clk: qcom: clk-alpha-pll: Check for the parent rate during round_rate

The parent rate passed in to the round_rate operation of the
alpha PLL could be 0. Account for this and fix the UBSAN warning:

UBSAN: Undefined behaviour in drivers/clk/qcom/clk-alpha-pll.c:311:137
division by zero

Change-Id: Ie6834a4e52589251fa7b7287ee292aafc92342a1
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
1 file changed