ARM: dts: msm: Add APSS CTI devices for SDM845
Add support for APSS CTI devices for SDM845.
Change-Id: I04d96b156d3f98c1fec38ac387ac11b7a1b75dfa
Signed-off-by: Satyajit Desai <sadesai@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
index ec0b328..4a15b01 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
@@ -1610,6 +1610,42 @@
clock-names = "apb_pclk";
};
+ cti0_apss: cti@78e0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b966>;
+ reg = <0x78e0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-APSS_CTI0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_apss: cti@78f0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b966>;
+ reg = <0x78f0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-APSS_CTI1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_apss: cti@7900000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b966>;
+ reg = <0x7900000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-APSS_CTI2";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
cti0: cti@6010000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x0003b966>;