ARM: dts: msm: Remove the csid clocks in phy for sdm845
Csid and csiphy are voting for the csid clock with different rates.
The clock will be turned ON by the csid, hence removing the
clocks from the csiphy.
Change-Id: Id86d847243a16ea52ec21a7fb189d0b4fd65ccfc
Signed-off-by: Soundrapandian Jeyaprakash <jsoundra@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
index cbd495a..3f19890 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
@@ -36,9 +36,7 @@
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY0_CLK>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
- <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
- <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
- <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>;
+ <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
@@ -46,12 +44,10 @@
"cphy_rx_clk_src",
"csiphy0_clk",
"csi0phytimer_clk_src",
- "csi0phytimer_clk",
- "ife_0_csid_clk",
- "ife_0_csid_clk_src";
+ "csi0phytimer_clk";
clock-cntl-level = "turbo";
clock-rates =
- <0 0 0 0 320000000 0 269333333 0 0 384000000>;
+ <0 0 0 0 320000000 0 269333333 0>;
status = "ok";
};
@@ -74,9 +70,7 @@
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY1_CLK>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
- <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
- <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
- <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>;
+ <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
@@ -84,12 +78,10 @@
"cphy_rx_clk_src",
"csiphy1_clk",
"csi1phytimer_clk_src",
- "csi1phytimer_clk",
- "ife_1_csid_clk",
- "ife_1_csid_clk_src";
+ "csi1phytimer_clk";
clock-cntl-level = "turbo";
clock-rates =
- <0 0 0 0 320000000 0 269333333 0 0 384000000>;
+ <0 0 0 0 320000000 0 269333333 0>;
status = "ok";
};
@@ -113,9 +105,7 @@
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY2_CLK>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
- <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
- <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
- <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>;
+ <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
@@ -123,12 +113,10 @@
"cphy_rx_clk_src",
"csiphy2_clk",
"csi2phytimer_clk_src",
- "csi2phytimer_clk",
- "ife_lite_csid_clk",
- "ife_lite_csid_clk_src";
+ "csi2phytimer_clk";
clock-cntl-level = "turbo";
clock-rates =
- <0 0 0 0 320000000 0 269333333 0 0 384000000>;
+ <0 0 0 0 320000000 0 269333333 0>;
status = "ok";
};