tree 7c91f5af0e59c1d2f213335ae5f57bb8e7908372
parent 99222c9e4de7feb22c93b19a92b35fcdad73ed42
author Xing Zheng <zhengxing@rock-chips.com> 1452169054 +0800
committer Heiko Stuebner <heiko@sntech.de> 1452956481 +0100

clk: rockchip: rk3036: fix uarts clock error

Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>