ASoC: clean up wm8974 and wm8978 clock divider handling
wm8974 and wm8978 codec drivers control DAC and ADC oversampling rates in their
.set_clkdiv() methods, which is wrong, because these are simple boolean
switches and not clock dividers. Move these bits to sound controls. Also remove
manual configuration of the MCLK divider in wm8978, since it is configured
automatically.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
diff --git a/sound/soc/codecs/wm8974.h b/sound/soc/codecs/wm8974.h
index 98de956..896a7f0 100644
--- a/sound/soc/codecs/wm8974.h
+++ b/sound/soc/codecs/wm8974.h
@@ -57,17 +57,7 @@
/* Clock divider Id's */
#define WM8974_OPCLKDIV 0
#define WM8974_MCLKDIV 1
-#define WM8974_ADCCLK 2
-#define WM8974_DACCLK 3
-#define WM8974_BCLKDIV 4
-
-/* DAC clock dividers */
-#define WM8974_DACCLK_F2 (1 << 3)
-#define WM8974_DACCLK_F4 (0 << 3)
-
-/* ADC clock dividers */
-#define WM8974_ADCCLK_F2 (1 << 3)
-#define WM8974_ADCCLK_F4 (0 << 3)
+#define WM8974_BCLKDIV 2
/* PLL Out dividers */
#define WM8974_OPCLKDIV_1 (0 << 4)