ASoC: clean up wm8974 and wm8978 clock divider handling
wm8974 and wm8978 codec drivers control DAC and ADC oversampling rates in their
.set_clkdiv() methods, which is wrong, because these are simple boolean
switches and not clock dividers. Move these bits to sound controls. Also remove
manual configuration of the MCLK divider in wm8978, since it is configured
automatically.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c
index 8dcebaa8..ec2624b 100644
--- a/sound/soc/codecs/wm8978.c
+++ b/sound/soc/codecs/wm8978.c
@@ -210,6 +210,10 @@
/* Speaker */
SOC_DOUBLE_R("Speaker Switch",
WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
+
+ /* DAC / ADC oversampling */
+ SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0),
+ SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0),
};
/* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
@@ -513,21 +517,6 @@
if (wm8978->f_mclk)
ret = wm8978_configure_pll(codec);
break;
- case WM8978_MCLKDIV:
- if (div & ~0xe0)
- return -EINVAL;
- snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, div);
- break;
- case WM8978_ADCCLK:
- if (div & ~8)
- return -EINVAL;
- snd_soc_update_bits(codec, WM8978_ADC_CONTROL, 8, div);
- break;
- case WM8978_DACCLK:
- if (div & ~8)
- return -EINVAL;
- snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 8, div);
- break;
case WM8978_BCLKDIV:
if (div & ~0x1c)
return -EINVAL;