tree 1039455d99febbc4bf86f80ecb5384b08329160d
parent 7bd688cd66db93f6430f6e2b3145ee5686daa315
author Jani Nikula <jani.nikula@intel.com> 1383922137 +0200
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1384337782 +0100

drm/i915: fix gen2-gen3 backlight set

Citing Jani's response to Imre's question in the review discussion:

> According to the gen2/3 bspec I have, the correct mask is
> BACKLIGHT_DUTY_CYCLE_MASK_PNV only in case of IS_PINEVIEW(dev), for
> everything else it's BACKLIGHT_DUTY_CYCLE_MASK.

What you say is correct, but we've treated all gen2/3 similar to PNV
since

commit ca88479c1c3b7b1a9f94320745f5331e1de77f80
Author: Keith Packard <keithp@keithp.com>
Date:   Fri Nov 18 11:09:24 2011 -0800

    drm/i915: Treat pre-gen4 backlight duty cycle value consistently

i.e. we only use the high 15 bits for all gen2/3. For non-PNV this just
means the lowest bit is always zero. For PNV the lowest bit has a
different meaning in both the PWM freq and duty cycle fields.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[danvet: Make the commit message less empty.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>