drm/msm/dsi-staging: toggle resync fifo after clock on
The resync retime FIFO in the DSI PHY needs to be toggled every time
there is a clock rate change in order to synchronize the data paths.
This FIFO should be toggled only after the display clock controller
sets the source for the DSI branch clocks to be the DSI PLL and the
enables the branch clock, otherwise it can lead to unintended
artifacts on the screen.
CRs-Fixed: 2196279
Change-Id: I3f5e230bff84e25f1644bf47cb6c5d975f1450eb
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
7 files changed