drm/msm/dsi-staging: toggle resync fifo after clock on
The resync retime FIFO in the DSI PHY needs to be toggled every time
there is a clock rate change in order to synchronize the data paths.
This FIFO should be toggled only after the display clock controller
sets the source for the DSI branch clocks to be the DSI PLL and the
enables the branch clock, otherwise it can lead to unintended
artifacts on the screen.
CRs-Fixed: 2196279
Change-Id: I3f5e230bff84e25f1644bf47cb6c5d975f1450eb
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
index f2c2985..2922c6c 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -213,6 +213,7 @@
dsi_phy_hw_v3_0_is_lanes_in_ulps;
phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v3_0;
phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset;
+ phy->ops.toggle_resync_fifo = dsi_phy_hw_v3_0_toggle_resync_fifo;
}
/**
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
index f7756dc..ddf9e84 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -103,6 +103,7 @@
int dsi_phy_hw_timing_val_v3_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
u32 *timing_val, u32 size);
int dsi_phy_hw_v3_0_lane_reset(struct dsi_phy_hw *phy);
+void dsi_phy_hw_v3_0_toggle_resync_fifo(struct dsi_phy_hw *phy);
/* DSI controller common ops */
u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index ff2c9ce..8921332 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -2159,6 +2159,20 @@
return 0;
}
+static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
+{
+ struct dsi_display_ctrl *ctrl;
+ int i;
+
+ if (!display)
+ return;
+
+ for (i = 0; i < display->ctrl_count; i++) {
+ ctrl = &display->ctrl[i];
+ dsi_phy_toggle_resync_fifo(ctrl->phy);
+ }
+}
+
static int dsi_display_ctrl_update(struct dsi_display *display)
{
int rc = 0;
@@ -3084,6 +3098,15 @@
dsi_display_ctrl_irq_update(display, true);
}
if (clk & DSI_LINK_CLK) {
+ /*
+ * Toggle the resync FIFO everytime clock changes, except
+ * when cont-splash screen transition is going on.
+ * Toggling resync FIFO during cont splash transition
+ * can lead to blinks on the display.
+ */
+ if (!display->is_cont_splash_enabled)
+ dsi_display_toggle_resync_fifo(display);
+
if (display->ulps_enabled) {
rc = dsi_display_set_ulps(display, false);
if (rc) {
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
index cc74de2..6a7a84c 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -752,6 +752,16 @@
return 0;
}
+void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy)
+{
+ if (!phy)
+ return;
+
+ if (!phy->hw.ops.toggle_resync_fifo)
+ return;
+
+ phy->hw.ops.toggle_resync_fifo(&phy->hw);
+}
int dsi_phy_set_ulps(struct msm_dsi_phy *phy, struct dsi_host_config *config,
bool enable, bool clamp_enabled)
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h
index a158812..56d5ee3 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -250,6 +250,16 @@
int dsi_phy_lane_reset(struct msm_dsi_phy *phy);
/**
+ * dsi_phy_toggle_resync_fifo() - toggle resync retime FIFO
+ * @phy: DSI PHY handle
+ *
+ * Toggle the resync retime FIFO to synchronize the data paths.
+ * This should be done everytime there is a change in the link clock
+ * rate
+ */
+void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy);
+
+/**
* dsi_phy_drv_register() - register platform driver for dsi phy
*/
void dsi_phy_drv_register(void);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h
index efebd99..e31899d4 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -240,6 +240,13 @@
*/
int (*phy_lane_reset)(struct dsi_phy_hw *phy);
+ /**
+ * toggle_resync_fifo() - toggle resync retime FIFO to sync data paths
+ * @phy: Pointer to DSI PHY hardware object.
+ * Return: error code.
+ */
+ void (*toggle_resync_fifo)(struct dsi_phy_hw *phy);
+
void *timing_ops;
struct phy_ulps_config_ops ulps_ops;
};
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c
index 8d91141..b078231 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -118,6 +118,15 @@
/* Nothing to be done for DSI PHY regulator disable */
}
+void dsi_phy_hw_v3_0_toggle_resync_fifo(struct dsi_phy_hw *phy)
+{
+ DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x00);
+ /* ensure that the FIFO is off */
+ wmb();
+ DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x1);
+ /* ensure that the FIFO is toggled back on */
+ wmb();
+}
static int dsi_phy_hw_v3_0_is_pll_on(struct dsi_phy_hw *phy)
{