| commit | b492b8744da9b205b9b303b111a138b16d56e712 | [log] [tgz] |
|---|---|---|
| author | Akshay Bhat <akshay.bhat@timesys.com> | Mon Apr 18 17:19:44 2016 -0400 |
| committer | Shawn Guo <shawnguo@kernel.org> | Tue Apr 26 11:05:30 2016 +0800 |
| tree | a5f5917a3a7303f3d56f5fe20f4cfd023d8e37cb | |
| parent | 7532c98f3ac212ca1f19be7e628356247b616c74 [diff] |
ARM: dts: imx6q-b850v3: Update display clock source The default monitor that ships with B850v3 requires a 65MHz pixel clock. 65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx, set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous display on both LVDS and HDMI interface. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>