tree 8f0da9ecb33e1d8c5651945dfaac9429bef5c27d
parent 4676f0aab9dc4f9aa729d5a5b75d20f824d77742
author Marek Szyprowski <m.szyprowski@samsung.com> 1411388232 +0200
committer Tomasz Figa <tomasz.figa@gmail.com> 1411389079 +0200

clk: samsung: exynos4: fix g3d clocks

sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because
it does not make any sense and most likely has been added by mistake.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
[tomasz.figa@gmail.com: Adjusted commit message.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>